Nonvolatile memory devices such as electrically programmable read-only memories (EPROMS), electrically erasable programmable read only memories (EEPROMS) and flash memories include an array of nonvolatile memory cells and circuitry to access the array. Nonvolatile memory cells typically have a field effect transistor that includes a control gate to control operation of the memory cell and a floating gate to store data. Certain flash memory devices may incorporate multi-level cell (MLC) technology such that multiple bits of data may be stored in each memory cell. For example, a memory cell can store two bits of data via four bit patterns, namely 00, 01, 10 and 11. Each bit pattern may be represented by a state, such as a range of threshold voltages VT of the memory cell or the like.
In programming a flash memory, a selected wordline and a selected bitline are biased at determined voltages to program a given memory cell located at the intersection of the selected lines. However, during such programming, because the selected bitline is typically taken to a high voltage, deselected memory cells connected to the selected bitline also see a high voltage that is coupled to the floating gate of the cells, causing an initial drain turn on (IDTO) leakage current through the deselected cells. This leakage is significant and causes several adverse effects, including cycling performance degradation, increased die size, and lower read windows between voltage threshold levels of a selected cell (which is critical for MLC performance). Similar leakage currents can occur during other memory operations, such as during read, erase, and verify operations. Thus a need exists to improve the operation of such memory arrays.